Most integrated circuits (ICs) require one or more periodic toggling signals, known as clocks, to function. In the design of reliable, available, and serviceable (RAS) systems, clock fault detection is important for assessing system health and for triggering automatic corrective action, such as selecting a redundant clock source or transferring control to backup equipment.
Many circuits have been used for clock fault detection. One prior art example uses a delay line and flip-flop as shown in FIG. 1. This design, which comprises a delay line 10, multiplexer 12, pair of flip-flops 14a, 14b, inverter 16, and OR gate 18, has a low latency and does not require another clock. However, it suffers from several disadvantages. The delay line position selected by the multiplexer must be tuned for the clock frequency, which may not be known a priori. Variations in the delay line over process and temperature may require a calibration scheme. If a range of frequencies is required, the delay line requires a large number of taps. A multi-tap delay line primitive may not be available in all digital design libraries, and building a delay line from individual buffer or delay cells can make timing difficult to control.